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| INTEGRATED CIRCUITS DATA SHEET 74AHC259; 74AHCT259 8-bit addressable latch Product specification File under Integrated Circuits, IC06 2000 Mar 14 Philips Semiconductors Product specification 8-bit addressable latch FEATURES * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V * Balanced propagation delays * All inputs have Schmitt-trigger actions * Combines demultiplexer and 8-bit latch * Serial-to-parallel capability * Output from each storage bit available * Random (addressable) data entry * Easily expandable * Common reset input * Useful as a 3-to-8 active HIGH decoder * Inputs accept voltages higher than VCC * For AHC only: operates with CMOS input levels * For AHCT only: operates with TTL input levels * Specified from -40 to +85 C and from -40 to +125 C. DESCRIPTION 74AHC259; 74AHCT259 The 74AHC/AHCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in digital systems. The `259' are multifunctional devices capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The `259' also incorporates an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). The `259' has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the `259' as an address latch, changing more than one bit of the address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the `259'. 2000 Mar 14 2 Philips Semiconductors Product specification 8-bit addressable latch QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 3.0 ns. 74AHC259; 74AHCT259 TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay D to Qn An to Qn LE to Qn MR to Qn CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 VI = VCC or GND CL = 15 pF; VCC = 5 V 4.1 5.3 4.3 3.9 3.0 4.0 13 4.1 5.5 4.3 3.9 3.0 4.0 17 ns ns ns ns pF pF pF CONDITIONS AHC AHCT UNIT 2000 Mar 14 3 Philips Semiconductors Product specification 8-bit addressable latch FUNCTION TABLE See note 1. INPUTS OPERATING MODE MR reset L LE H D X d d demultiplexer (active HIGH 8-channel) decoder (when D = H) d L L d d d d d memory (do nothing) H H X d d d addressable latch H L d d d d H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; A0 X L H L H L H L H X L H L H L H L H A1 X L L H H L L H H X L L H H L L H H A2 X L L L L H H H H X L L L L H H H H Q0 L Q=d L L L L L L L q0 Q=d q0 q0 q0 q0 q0 q0 q0 Q1 L L Q=d L L L L L L q1 q1 Q=d q1 q1 q1 q1 q1 q1 Q2 L L L Q=d L L L L L q2 q2 q2 Q=d q2 q2 q2 q2 q2 Q3 L L L L Q=d L L L L q3 q3 q3 q3 Q=d q3 q3 q3 q3 Q4 L L L L L Q=d L L L q4 q4 q4 q4 q4 Q=d q4 q4 q4 OUTPUTS 74AHC259; 74AHCT259 Q5 L L L L L L Q=d L L q5 q5 q5 q5 q5 q5 Q=d q5 q5 Q6 L L L L L L L Q=d L q6 q6 q6 q6 q6 q6 q6 Q=d q6 Q7 L L L L L L L L Q=d q7 q7 q7 q7 q7 q7 q7 q7 Q=d q = lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. ORDERING INFORMATION PACKAGES TYPE NUMBER 74AHC259D 74AHC259PW 74AHCT259D 74AHCT259PW TEMPERATURE RANGE -40 to +125 C PINS 16 16 16 16 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT109-1 SOT403-1 SOT109-1 SOT403-1 2000 Mar 14 4 Philips Semiconductors Product specification 8-bit addressable latch PINNING PIN 1, 2 and 3 4, 5, 6, 7, 9, 10, 11 and 12 8 13 14 15 16 Q0 to Q7 GND D LE MR VCC SYMBOL A0, A1 and A2 74AHC259; 74AHCT259 DESCRIPTION address input latch outputs ground (0 V) data input latch enable input (active LOW) conditional reset input (active LOW) DC supply voltage handbook, halfpage A0 1 A1 2 A2 3 Q0 4 16 VCC 15 MR 14 LE 13 D handbook, halfpage 14 LE Q0 13 D Q1 Q2 Q3 1 2 3 A0 A1 A2 MR 15 MNA573 4 5 6 7 9 10 11 12 259 Q1 5 Q2 6 Q3 7 GND 8 MNA574 12 Q7 11 Q6 10 Q5 9 Q4 Q4 Q5 Q6 Q7 Fig.1 Pin configuration. Fig.2 Logic symbol. 2000 Mar 14 5 Philips Semiconductors Product specification 8-bit addressable latch 74AHC259; 74AHCT259 handbook, halfpage 13 15 14 Z9 G8 G10 9,10D 0 1 C10 8R handbook, halfpage Q0 DX 1 2 3 4 1 2 5 1 6 2 7 3 9 4 10 5 11 6 12 7 MNA572 MNA571 4 5 6 7 9 A0 A1 A2 1-of-8 DECODER 8 LATCHES Q1 Q2 Q3 Q4 0 G 2 0 7 3 14 15 13 LE MR D Q5 10 Q6 11 Q7 12 Fig.3 IEC logic symbol. Fig.4 Functional diagram. OPERATING MODE SELECT TABLE LE L H L H Note 1. H = HIGH voltage level; L = LOW voltage level. MR H H L L addressable latch memory active HIGH 8-channel demultiplexer reset MODE 2000 Mar 14 6 Philips Semiconductors Product specification 8-bit addressable latch RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature see DC and AC characteristics per device VCC = 3.3 0.3 V VCC = 5 0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40 - - TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 4.5 0 0 -40 74AHC259; 74AHCT259 74AHCT UNIT TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 V V V C +125 -40 100 20 - - +125 C - 20 ns/V ns/V tr, tf input rise and fall ratios (t/f) LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage DC input diode current DC output sink current DC VCC or GND current storage temperature power dissipation per package for temperature range: -40 to +125 C; note 2 VI < -0.5 V; note 1 -0.5 V < VO < VCC + 0.5 V DC output clamping diode current VO < -0.5 V or VO > VCC + 0.5 V; note 1 CONDITIONS MIN. MAX. UNIT -0.5 -0.5 - - - - -65 - +7.0 +7.0 -20 20 25 75 500 V V mA mA mA mA mW +150 C 2000 Mar 14 7 Philips Semiconductors Product specification 8-bit addressable latch DC CHARACTERISTICS 74AHC family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -4.0 mA VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 4.0 mA VI = VIH or VIL; IO = 8.0 mA II IOZ ICC CI input leakage current 3-state output OFF-state current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 - - - 1.9 2.9 4.4 - - - - - 2.0 3.0 4.5 25 TYP. - - - 0.5 0.9 1.65 - - - - - 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (C) -40 to +85 - - 0.5 0.9 1.65 - - - 74AHC259; 74AHCT259 -40 to +125 UNIT - - 0.5 0.9 1.65 - - - MAX. MIN. MAX. MIN. MAX. 1.5 2.1 - - - 1.9 2.9 4.4 1.5 2.1 - - - 1.9 2.9 4.4 V V V V V V V V V V V V V V V V A 3.85 - 3.85 - 3.85 - 2.58 - 3.94 - - - - - - - - - - 0 0 0 - - - - - 3 2.48 - 3.8 - - - - - - - 0.1 0.1 0.1 0.44 0.44 1.0 2.5 40 10 2.40 - 3.70 - - - - - - - - - - 0.1 0.1 0.1 0.55 0.55 2.0 VI = VIH or VIL; 5.5 VO = VCC or GND VI = VCC or GND; IO = 0 5.5 - 0.25 - 4.0 10 - - 10.0 A 80 10 A pF 2000 Mar 14 8 Philips Semiconductors Product specification 8-bit addressable latch 74AHCT family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 8.0 mA II IOZ input leakage current 3-state output OFF-state current VI = VIH or VIL VCC (V) - - 4.5 25 - 0.8 - - 0.1 0.36 0.1 Tamb (C) -40 to +85 - 0.8 - - 0.1 0.44 1.0 2.5 74AHC259; 74AHCT259 -40 to +125 UNIT - 0.8 - MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 - 4.4 3.8 - - - 2.0 - 4.4 V V V V V V A 4.5 to 5.5 2.0 4.5 to 5.5 - 4.5 4.5 4.5 4.5 5.5 4.4 3.94 - - - - - 0 - - - 3.70 - - - - - 0.1 0.55 2.0 VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC - 2.1 V other inputs at VCC or GND; IO = 0 0.25 - 10.0 A ICC ICC quiescent supply current additional quiescent supply current per input pin input capacitance - - - 4.0 1.35 - - 40 1.5 - - 80 1.5 A mA 4.5 to 5.5 - CI - - 3 10 - 10 - 10 pF 2000 Mar 14 9 Philips Semiconductors Product specification 8-bit addressable latch AC CHARACTERISTICS Type 74AHC259 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay see Figs 5 and 11 15 pF - D to Qn propagation delay see Figs 6 and 11 An to Qn propagation delay see Figs 7 and 11 LE to Qn tPHL tPHL/tPLH propagation delay see Figs 8 and 11 MR to Qn - - - 5.8 7.5 6.2 5.4 7.3 9.1 7.7 7.0 - - - - 11.5 14.5 12.0 10.5 14.5 18.0 15.5 13.5 - - - - 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 4.0 1.0 13.5 17.0 14.0 12.5 17.0 21.0 17.5 15.5 - - - - CL MIN. 25 TYP. Tamb (C) -40 to +85 MAX. MIN. MAX. 74AHC259; 74AHCT259 -40 to +125 MIN. MAX. UNIT 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 4.0 1.0 15.0 18.5 15.2 13.5 18.5 23.0 19.0 17.0 - - - - ns ns ns ns ns ns ns ns ns ns ns ns propagation delay see Figs 5 and 11 50 pF - D to Qn propagation delay see Figs 6 and 11 An to Qn propagation delay see Figs 7 and 11 LE to Qn - - - 5.0 5.0 4.0 1.0 tPHL tW propagation delay see Figs 8 and 11 MR to Qn LE pulse width HIGH or LOW MR pulse width LOW see Figs 7 and 11 see Figs 8 and 11 see Figs 9, 10 and 11 tsu th set-up time D to LE, An to LE hold time D to LE, see Figs 9 and 11 An to LE 2000 Mar 14 10 Philips Semiconductors Product specification 8-bit addressable latch 74AHC259; 74AHCT259 Tamb (C) 25 -40 to +85 MAX. MIN. MAX. -40 to +125 MIN. MAX. UNIT TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay see Figs 5 and 11 15 pF - D to Qn propagation delay see Figs 6 and 11 An to Qn propagation delay see Figs 7 and 11 LE to Qn tPHL tPHL/tPLH propagation delay see Figs 8 and 11 MR to Qn - - - 4.1 5.3 4.3 3.9 5.3 6.5 5.5 5.1 - - - - 7.5 9.5 8.0 7.0 9.5 11.5 10.0 9.0 - - - - CL MIN. TYP. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 4.0 1.0 9.0 11.5 9.5 8.5 11.0 13.5 11.5 10.5 - - - - 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 4.0 1.0 10.0 12.5 10.5 9.5 12.0 15.0 12.5 11.5 - - - - ns ns ns ns ns ns ns ns ns ns ns ns propagation delay see Figs 5 and 11 50 pF - D to Qn propagation delay see Figs 6 and 11 An to Qn propagation delay see Figs 7 and 11 LE to Qn - - - 5.0 5.0 4.0 1.0 tPHL tW propagation delay see Figs 8 and 11 MR to Qn LE pulse width HIGH or LOW MR pulse width LOW see Figs 7 and 11 see Figs 8 and 11 see Figs 9, 10 and 11 tsu th Notes set-up time D to LE, An to LE hold time D to LE, see Figs 9 and 11 An to LE 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 2000 Mar 14 11 Philips Semiconductors Product specification 8-bit addressable latch Type 74AHCT259 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay see Figs 5 and 11 15 pF - D to Qn propagation delay see Figs 6 and 11 An to Qn propagation delay see Figs 7 and 11 LE to Qn tPHL tPHL/tPLH propagation delay see Figs 8 and 11 MR to Qn - - - 4.1 5.5 4.3 3.9 5.4 6.6 5.5 5.1 - - - - 7.5 9.5 8.0 7.0 9.5 12.0 10.0 9.0 - - - - 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 4.0 1.0 9.0 11.5 9.5 8.5 11.0 14.0 12.0 10.5 - - - - CL MIN. 25 TYP. Tamb (C) -40 to +85 MAX. MIN. MAX. 74AHC259; 74AHCT259 -40 to +125 MIN. MAX. UNIT 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 4.0 1.0 10.0 12.5 10.4 9.5 12.0 15.5 13.0 11.5 - - - - ns ns ns ns ns ns ns ns ns ns ns ns propagation delay see Figs 5 and 11 50 pF - D to Qn propagation delay see Figs 6 and 11 An to Qn propagation delay see Figs 7 and 11 LE to Qn - - - 5.0 5.0 4.0 1.0 tPHL tW propagation delay see Figs 8 and 11 MR to Qn LE pulse width HIGH or LOW MR pulse width LOW see Figs 7 and 11 see Figs 8 and 11 tsu th Note set-up time see Figs 9, D to LE, An to LE 10 and 11 hold time D to LE, see Figs 9 and 11 An to LE 1. Typical values at VCC = 5.0 V. 2000 Mar 14 12 Philips Semiconductors Product specification 8-bit addressable latch AC WAVEFORMS 74AHC259; 74AHCT259 V handbook, halfpage CC D input GND t PHL VOH Qn output VOL VM(2) MNA569 V handbook, halfpage CC VM(1) An input GND t PLH VOH Qn output VOL VM(2) MNA568 VM(1) t PHL t PLH FAMILY AHC AHCT Fig.5 VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 1.5 V VM(2) OUTPUT 50% VCC FAMILY AHC AHCT Fig.6 VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 1.5 V VM(2) OUTPUT 50% VCC 50% VCC 50% VCC 50% VCC 50% VCC The data input (D) to output (Qn) propagation delays. The address input (An) to output (Qn) propagation delays. handbook, full pagewidth VCC D input GND VCC LE input GND tW t PHL VOH Qn output VOL VM(2) MNA570 VM(1) t PLH FAMILY AHC AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 1.5 V VM(2) OUTPUT 50% VCC 50% VCC 50% VCC Fig.7 The enable input (LE) to output (Qn) propagation delays, the enable input pulse width. 2000 Mar 14 13 Philips Semiconductors Product specification 8-bit addressable latch 74AHC259; 74AHCT259 handbook, halfpage VCC VCC handbook, halfpage VM(1) An input GND tW t PHL VCC LE input VM(2) GND MNA548 MR input GND VM(1) ADDRESS STABLE t su th VOH Qn output VOL VM(1) MNA550 The shaded areas indicate when the input is permitted to change for predictable output performance. FAMILY AHC AHCT Fig.8 VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 1.5 V VM(2) OUTPUT 50% VCC FAMILY AHC AHCT Fig.9 VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 50% VCC 1.5 V 50% VCC 50% VCC The conditional reset input (MR) to output (Qn) propagation delays. The address set-up and hold time for An inputs to LE input. handbook, full pagewidth VCC LE input GND t su th VCC D input GND VM(1) t su th VM(1) VOH Qn output VOL Q=D VM(2) Q=D MNA549 FAMILY AHC AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 1.5 V VM(2) OUTPUT 50% VCC The shaded areas indicate when the input is permitted to change for predictable output performance. 50% VCC 50% VCC Fig.10 The data set-up and hold time for D input to LE input. 2000 Mar 14 14 Philips Semiconductors Product specification 8-bit addressable latch 74AHC259; 74AHCT259 handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL MNA219 VO 1000 VCC open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND S1 Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter "AC characteristics"). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.11 Load circuitry for switching times. 2000 Mar 14 15 Philips Semiconductors Product specification 8-bit addressable latch PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm 74AHC259; 74AHCT259 SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 0.010 0.057 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 8 0o o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 2000 Mar 14 16 Philips Semiconductors Product specification 8-bit addressable latch 74AHC259; 74AHCT259 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27 2000 Mar 14 17 Philips Semiconductors Product specification 8-bit addressable latch SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering 74AHC259; 74AHCT259 If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2000 Mar 14 18 Philips Semiconductors Product specification 8-bit addressable latch Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable 74AHC259; 74AHCT259 REFLOW(1) 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. 2000 Mar 14 19 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 69 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613507/01/pp20 Date of release: 2000 Mar 14 Document order number: 9397 750 06821 |
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